Methods and apparatus for address generation in processors
US7269711B2 · kind B2 · utility
2Cited by
8References
41Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2003 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Mar 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus to generate addresses in processors are disclosed. An example address generator disclosed herein includes an adder to add a first address component and a second address component to generate an address, a correction indicator to indicate if the address is correct, and a control input to modify an operation of the adder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.