Adjusting thread instruction issue rate based on deviation of actual executed number from intended rate cumulative number
US7269713B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2002 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Jun 29, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for controlling issue rate of instructions for an instruction thread to be executed by a processor is provided. The rate at which instructions are to be executed for an instruction thread are stored (46) and requests are issued (44) to cause instructions to execute in response to the stored rate. The rate at which instruction requests are issued is reduced in response to instruction executions and is increased in the absence of instruction executions. In a multi-threaded processor, instruction rate is controlled by storing the average rate at which each thread should execute instructions (48). A value representative of the number of instructions available and not yet issued is monitored and is decreased in response to instruction executions (42). Execution of instructions is prevented on a thread if the number of instructions available but not yet issued falls below a defined value. A ranking order is assigned to a plurality of instructions threads for execution on a multi-threaded processor. A plurality of metrics related to the threads and required for establishment of the rank order are provided. Each metric is assigned to a set of bits and these are assem…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.