Method and apparatus for flexible and programmable clock crossing control with dynamic compensation
US7269754B2 · kind B2 · utility
35Cited by
7References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2002 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Jun 7, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to selectively input a source clock pulse. The outputs of the latch components may be selected by a multiplexor according to the phases of the destination clock. In another embodiment, a time delay may be passed into the destination clock domain and may be calculated by a number of destination clock cycle time periods. In certain circumstances, the time delay may be adjusted to compensate for longer delays in the clock crossing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.