Solid-state memory device with protection against power failure
US7269755B2 · kind B2 · utility
83Cited by
5References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 26, 2006 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Jul 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data preservation system for flash memory systems with a host system, the flash memory system receiving a host system power supply and energizing an auxiliary energy store therewith and communicating with the host system via an interface bus, wherein, upon loss of the host system power supply, the flash memory system actively isolates the connection to the host system power supply and isolates the interface bus and employs the supplemental energy store to continue write operations to flash memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.