Apparatus and method for performing bit de-collection in a communication system using a high speed downlink packet access (HSDPA) scheme
US7269776B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2004 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Dec 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/1812
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus and a method for performing a bit de-collection according to a hybrid automatic retransmission request are disclosed. The apparatus includes a column counter for increasing one column every four bits and outputting a position of a current column in response to received bit sequences; a state detector for outputting state information of the current column by means of an output value of the column counter, a parameter denoting a number of rows to which systematic bits have been assigned, and a parameter denoting a number of columns to which the systematic bits have been assigned; and address generators for generating write addresses required for performing a write operation and read addresses required for performing a read operation according to the state information output from the state detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.