System and method for mapping logical components to physical locations in an integrated circuit design environment
US7269803B2 · kind B2 · utility
117Cited by
22References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2003 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Sep 16, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for mapping Intellectual Property (IP) components onto a pre-fabricated chip slice allows a user to select a target location for placement of an IP component onto a slice. A slice definition of the pre-fabricated chip slice is searched for a legal location for the IP component that is near to the target location. The IP component is mapped to the legal location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.