Manufacturing process of a stacked semiconductor device
US7269897B2 · kind B2 · utility
5Cited by
7References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 23, 2003 |
| Grant date | Sep 18, 2007 |
| Priority date | — |
| Expiry date | Mar 13, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49137
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing process of a stacked semiconductor device, comprising the following steps: integrating a plurality of electronic devices in a plurality of active areas realized in a semiconductor wafer; distributing an adhesive layer on active areas, splitting the semiconductor wafer into a plurality of first dies, each one comprising at least one of the active areas; mounting the plurality of first dies, which are already equipped with the adhesive layer, on a support; and mounting a plurality of second dies on the adhesive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.