High speed amplifier incorporating pre-emphasis
US7271659B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Nov 24, 2004 |
| Grant date | Sep 18, 2007 |
| Priority date | — |
| Expiry date | Nov 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00208
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier circuit for receiving an input signal and providing an output signal, comprises a main chain of logic stages with a plurality of nodes therebetween, and at least one auxiliary chain nested between one node in the main chain and another node, which is not the next node, to form a series of feed back or feed forward nested equalisation loops; whereby the input signal is fed serially down the main chain and is also fed through the said at least one auxiliary chain and summed to provide the output signal. The invention overcomes gain-bandwidth limits of the drive stages and bandwidth reductions that occur when analogue stages operating in a linear mode are concatenated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.