Digital BIST test scheme for ADC/DAC circuits
US7271751B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2006 |
| Grant date | Sep 18, 2007 |
| Priority date | — |
| Expiry date | Feb 8, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A generalized method for testing DACs (Digital to Analog Converters) and ADCs (Analog to Digital Converters), such as Sigma Delta (Successive Approximation), Pipeline or Flash ADCs. The DACs and ADCs are tested in pairs using a Digital Tester and on chip test circuitry. The DACs and ADCs may be tested at the highest clock frequency allowed in the specification, shortening test time. The test circuits required for this test scheme comprise cell logic two multiplexer cells and an internal Analog Test Bus. This scheme is extendable to the testing of many DACs and ADCs on the same IC. The number of DACs and ADCs need not be equal. Furthermore, the DACs may have more (or less) bits (addresses) than the ADCs. An ADC may be tested with more than one DAC or vice versa to determine which cell is at fault if a test fails.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.