Generating adjustable-delay clock signal for processing color signals
US7271788B2 · kind B2 · utility
3Cited by
5References
29Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 20, 2003 |
| Grant date | Sep 18, 2007 |
| Priority date | — |
| Expiry date | Mar 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0322
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits, devices and methods provide a phase delay and use it to select when an analog color signal is converted to digital. The phase delay is adjustable, which permits choosing a moment in time when conversion results in improved processing. A PLL circuit receives the synchronizing signal of the color signals, and generates phased signals. A phase adjuster generates an adjustable delay signal by mixing in suitable proportions two of the phased signals that are 45 degrees apart. The delay signal is used by an analog to digital converter, to adjust when exactly it is to be sampled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.