Image display control method and image display control apparatus
US7271808B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2004 |
| Grant date | Sep 18, 2007 |
| Priority date | — |
| Expiry date | Feb 1, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/147
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
When a contention is detected between a memory write address and a display read address in a memory circuit which stores display data, a host retry pulse generating circuit generates a display read signal and a display line data transfer signal based on a memory write clock, and supplies these to the memory circuit while supplying the display line data transfer signal to a line latch circuit. Alternatively, upon detection of the contention above, a same line re-display read processing circuit performs same line re-display read processing without moving to the next line, and supplies a display read signal and a display line data transfer signal to the memory circuit while supplying the display line data transfer signal to the line latch circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.