Digital signal processor implementation of high impedance fault algorithms
US7272515B2 · kind B2 · utility
2Cited by
5References
11Claims
0Family size
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Key dates
| Filing date | Mar 15, 2005 |
| Grant date | Sep 18, 2007 |
| Priority date | — |
| Expiry date | Mar 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H1/0092
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A digital signal processor implementation of three algorithms used to detect high impedance faults. The algorithms can be wavelet based, higher order statistics based and neural network based. The algorithms are modified to process one second of data instead of ten seconds of data and a double buffered acquisition is connected to the output of the algorithms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.