Exploitive test pattern apparatus and method
US7272756B2 · kind B2 · utility
11Cited by
19References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 3, 2005 |
| Grant date | Sep 18, 2007 |
| Priority date | — |
| Expiry date | Oct 19, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Communications equipment can be tested using a test pattern that is modified compared to, and more exploitive than, a standard test pattern. Test patterns can be employed that have lengthened or shortened consecutive identical digit (CID) portions, or that have lengthened or shortened pseudo random bit sequence (PRBS) portions. In some cases, PRBS polynomials are not re-seeded after each CID. Further, different order polynomials can be employed for different applications. Exemplary applications can include test equipment and built-in self-test capability for integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.