Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit
US7272761B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2004 |
| Grant date | Sep 18, 2007 |
| Priority date | — |
| Expiry date | Jun 9, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318547
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of controlling test data with a boundary latch module having a plurality of latches to facilitate logic built-in self-testing of an integrated circuit (IC) is provided which includes providing a plurality of selection devices for selecting initialization data to store in the plurality of latches of the IC's boundary latch module. The initialization data is selected from a plurality of scan paths of the integrated circuit, and the initialization data from at least one of the latches is provided as input to a logic circuit of the IC or output of the IC. In another aspect, the method includes selecting a datum from an external input or test-pattern generator of the integrated circuit for capture in at least one of the latches and input to a multiple-input signature register, which stores a signature of the integrated circuit resulting from the logic built-in self-testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.