Generation of RTL to carry out parallel arithmetic operations
US7272804B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 28, 2005 |
| Grant date | Sep 18, 2007 |
| Priority date | — |
| Expiry date | Nov 7, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer-implemented method and system for generating an optimized description of an arithmetic function comprising at least two of an addition, a multiplication, and a rounding operation to be carried out on a plurality of data bits in a plurality of registers of an electronic circuit, the method comprising the steps: obtaining a first description of the arithmetic function; decomposing the first description to obtain a second description comprising individual binary and logical operations on data bits, wherein the data bits are arranged to their proper place value, the second description being substantially arithmetically equivalent to the first description; obtaining a third description by parallelizing at least two of the binary and logical operations on the data bits in the second description; providing a forth description comprising operations for each data bit comprised in the third description in a hardware description language as the optimized description of the electronic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.