Automatic layout method of semiconductor integrated circuit
US7272811B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2005 |
| Grant date | Sep 18, 2007 |
| Priority date | — |
| Expiry date | Dec 12, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An automatic layout method of a semiconductor integrated circuit includes an initial arranging step for initially arranging a logic cell which constitutes the logic circuit; a placement base circuit optimizing step for applying a margin of a constant length to a wiring line length obtained from a placement so as to improve timing; an placement change restriction calculating step for calculating a placement change restriction corresponding to the margin of the constant length; and an incremental arranging step in which when a logic cell placement of a corrected logic circuit is improved, a placement improvement having the placement change restriction calculated based upon the placement change restriction calculating step is carried out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.