Nanoscale wire-based sublithographic programmable logic arrays
US7274208B2 · kind B2 · utility
19Cited by
7References
87Claims
0Family size
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Key dates
| Filing date | May 28, 2004 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | Aug 9, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/81
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and methods for a sublithographic programmable logic array (PLA) are disclosed. The apparatus allows combination of non-restoring, programmable junctions and fixed (non-programmable) restoration logic to implement any logic function or any finite-state machine. The methods disclosed teach how to integrate fixed, restoration logic at sublithographic scales along with programmable junctions. The methods further teach how to integrate addressing from the microscale so that the nanoscale crosspoint junctions can be programmed after fabrication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.