Low jitter frequency synthesizer
US7274231B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2005 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | Sep 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0805
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency synthesizer IC is disclosed that includes a variable delay circuit, a fractional-N phase locked loop circuit, and a feedback loop. The variable delay circuit is electrically coupled to the input of the fractional-N phase locked loop circuit. The feedback loop couples a first control signal from the fractional-N phase locked loop to the variable delay circuit. The variable delay circuit generates a reference signal that has a phase delay that varies in accordance with a second control signal and a first control signal. The fractional-N phase locked loop circuit is operable upon receiving the reference signal to generate the first control signal, the second control signal, and an output signal having a frequency that is a non-integer product of the reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.