Digital circuit having delay circuit for adjustment of clock signal timing
US7274238B2 · kind B2 · utility
2Cited by
14References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2003 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | Nov 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital circuit according to the present invention includes a pulse delay circuit where a driving current of an inverter is variable, for causing timing of a clock signal to be variable; and the pulse delay circuit has a stabilizing circuit for an amount of a pulse delay by a delay synchronizing loop, and a generating circuit for a pulse delay amount setting voltage with nonlinear characteristics. The present invention makes it possible to realize a timing delay circuit with high resolution, which is not influenced by an operating environment and requires only a small area for the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.