ESD clamp with “trailing pulse” suppression
US7274545B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2005 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | Oct 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
In a method and system for protecting a semiconductor device from an electrostatic discharge (ESD) event, an ESD tester generates an ESD event by providing an ESD test signal having a leading pulse and a trailing pulse. An ESD input of the device under test (DUT) receives the ESD test signal. An ESD protection circuit embedded in the DUT detects the ESD signal and asserts a trigger in response to the detection. The ESD protection circuit provides a leading discharge path to the leading pulse in response to detecting the ESD signal, thereby protecting the DUT during the leading pulse. In addition, the ESD protection circuit also provides a trailing discharge path to the trailing pulse in response to the trigger, thereby protecting the DUT during the trailing pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.