Array fault testing approach for TCAMs
US7274581B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2006 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | May 4, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel array fault testing for a TCAM system that includes a plurality of TCAM blocks that is organized into at least one rectangular array having rows each having a plurality of TCAM blocks, a group of TCAM cells and associated read/write bit lines connecting the group of TCAM cells to write driver and decoding block. The data decode bypass circuit of the TCAM cell provides a raw write feature to detect faults in a full suite of memory related tests. The debug input of the data debug bypass circuit of the TCAM cell when asserted in the test mode enables the TCAM cell to write raw, unencoded data into the array, and when deasserted in the test mode, enables the testing of the TCAM array. The resulting TCAM cell provides exhaustive fault testing thereby detecting and eliminating faults in TCAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.