Memory system having multi-terminated multi-drop bus
US7274583B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2005 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | Nov 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a memory system having a multi-drop bus structure. The memory system includes a bus, a memory controller in which a port connected to the bus is terminated by a resistor having a first impedance value, a connector connected to a point having the first impedance value from the memory controller on a bus line, and a memory module connected to the connector. The memory module includes a first load connected to the connector and having the first impedance value, a second load connected to the first load and having a second impedance value, a first chip in which a port connected to the second load is terminated by a resistor having the second impedance value, a via hole penetrating a printed circuit board of the memory module between the first load and the second load, a third load connected to the via hole and having the second impedance value, and a second chip in which a port connected to the third load is terminated by a resistor having the second impedance value. The first load, the second load, and a first chip are formed on a first surface of the memory module while the third load and the second chip are formed on a second surface thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.