Integrated circuit apparatus
US7274616B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2006 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | Jan 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit apparatus includes a SRAM cell array having a plurality of memory cells formed of CMOSFET arranged lattice-like. The SRAM cell array has a pair of power line and ground line in each of 1-bit sequences. The integrated circuit apparatus also includes a detector detecting the occurrence of latch-up for each 1-bit sequence and outputting a detection signal, and a power controller controlling a power supply voltage to the power line for each 1-bit sequence. The power controller reduces a voltage to be supplied to the power line in the 1-bit sequence where latch-up is occurring down to a predetermined value according to the detection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.