Fast pattern processor including a function interface system
US7275117B2 · kind B2 · utility
1Cited by
40References
10Claims
0Family size
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Key dates
| Filing date | Sep 28, 2005 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | Mar 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3018
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A fast pattern processor having an internal function bus and an external function bus. In one embodiment, a fast pattern processor includes: (1) an internal function bus, (2) an external function bus, (3) a context memory having a block buffer and a argument signature register wherein the block buffer includes processing blocks associated with a protocol data unit (PDU), (4) a pattern processing engine, associated with the context memory, that performs pattern matching and (5) a function interface system having (5A) a controller arbitration subsystem and (5B) a dispatch subsystem.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.