Configurable advanced technology attachment/integrated drive electronics host controller with programmable timing registers that store timing parameters that control communications
US7275120B2 · kind B2 · utility
3Cited by
4References
19Claims
0Family size
Inventors
Key dates
| Filing date | May 14, 2004 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | Sep 7, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An ATA/IDE host controller 100 generated from an HDL design base and a default frequency configuration script is disclosed. The controller supports ATA/IDE interface communications at a user-selected default frequency of 33, 66, 100, or 133 Mhz and at frequencies other than the default frequency using a set of programmable override timing registers 121. An internal timing control module 110 provides either the default timing parameters or the override timing parameters to the IDE host interface 102, according to the programmable override control 301.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.