Accessing multiple copies of RAM distributed throughout an ASIC/FPGA and maintaining their content consistency
US7275129B1 · kind B1 · utility
1Cited by
1References
13Claims
0Family size
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Key dates
| Filing date | Jan 30, 2004 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | Feb 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for writing the same data field to multiple RAM copies during a single write cycle that fans out write data, address data, and control data to multiple RAMs. The multiple copies of data held at the same address in the multiple RAM copies are also read during a single write cycle and the data from each RAM copy is concatenated into a single word that is read during a single read cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.