Method and apparatus for a modified parity check
US7275199B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2004 |
| Grant date | Sep 25, 2007 |
| Priority date | — |
| Expiry date | Dec 1, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, an apparatus, and a computer program are provided for sequentially determining parity of stored data. Because of the inherent instabilities that exist in most memory arrays, data corruption can be a substantial problem. Parity checking and other techniques are typically employed to counteract the problem. However, with parity checking and other techniques, there are tradeoffs. Time required to perform the parity check, for example, can cause system latencies. Therefore, to reduce latencies, a trusted register can be included into a memory system to allow for immediate access to one piece of trusted data. By being able to read one piece of trusted data, the system can overlap the parity checking and delivery of a location of data with the reading of the next location of data from the memory array. Hence, a full cycle of latency can be eliminated without the reduction of the clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.