Method for fabricating semiconductor device
US7276407B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2005 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Sep 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
Abstract
A method for fabricating a semiconductor device including on a single semiconductor substrate, a first MOS transistor having a first gate insulating film of a predetermined thickness, and second and third MOS transistors sharing a second gate insulating film smaller in thickness than the first gate insulating film, the third MOS transistor being lower in threshold voltage than the second MOS transistor, the method includes the steps of: adjusting the threshold voltages of the first and third MOS transistors by first ion-implantation; and adjusting the threshold voltage of the second MOS transistor by second ion-implantation, the second ion-implantation being performed under implantation conditions different from those of the first ion-implantation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.