Semiconductor device having a pixel matrix circuit that includes a pixel TFT and a storage capacitor
US7276730B2 · kind B2 · utility
31Cited by
57References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2001 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Apr 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
In a CMOS circuit formed on a substrate 100, a subordinate gate wiring line (a first wiring line) 102a and main gate wiring line (a second wiring line) 113a are provided in an n-channel TFT. The LDD regions 107a and 107b overlap the first wiring line 102a and not overlap the second wiring line 113a. Thus, applying a gate voltage to the first wiring line forms the GOLD structure, while not applying forms the LLD structure. In this way, the GOLD structure and the LLD structure can be used appropriately in accordance with the respective specifications required for the circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.