Non-volatile electrically alterable semiconductor memory with control and floating gates and side-wall coupling
US7276759B1 · kind B1 · utility
5Cited by
9References
20Claims
0Family size
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Key dates
| Filing date | Mar 11, 2004 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | May 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
In a memory cell array, each memory cell includes a control gate disposed laterally adjacent a floating gate. The memory cells in each memory column are disposed inside a single well. The control gate and the floating gate are disposed between two diffusion regions. Each memory cell may be erased and programmed by applying a combination of voltages to the diffusion regions, the control gate, and the well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.