Junction-isolated vias
US7276794B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 2, 2005 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Jul 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming a junction-isolated, electrically conductive via in a silicon substrate and a conductive apparatus to carry electrical signal from one side of a silicon wafer to the other side are provided. The conductive via is junction-isolated from the bulk of the silicon substrate by diffusing the via with a dopant that is different than the material of the silicon substrate. Several of the junction-isolated vias can be formed in a silicon substrate and the silicon wafer coupled to a second silicon substrate of a device that requires electrical connection. This process for forming junction-isolated, conductive vias is simpler than methods of forming metallized vias, especially for electrical devices more tolerant of both resistance and capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.