Interlocking memory/logic cell layout and method of manufacture
US7277309B1 · kind B1 · utility
11Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2006 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Oct 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory/logic cell layout structure includes a pair of memory/logic cells formed on a substrate. Each memory/logic cell (102, 104) can include a pair of memory areas to store data (106-0/106-1, 106-2/106-3), and a logic portion (108-0, 108-1) that receives the data stored therein. Memory areas and the logic portions of each memory/logic cell can be arranged on the substrate in a shape of an L, U, S, T, or Z to form a pair of interlocking memory/logic cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.