MRAM architecture for low power consumption and high selectivity
US7277317B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 14, 2004 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | May 22, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a magnetoresistive memory cell (30), comprising a magnetoresistive memory element (31), a first current line (32) and a second current line (33), the first and the second current line (32, 33) crossing each other at a cross-point region but not being in direct contact. According to the invention, a bridging element(34) connects the first and second current lines (32, 33) in the vicinity of the cross-point region. The bridging element (34) is magnetically couplable to the magnetoresistive memory element (31). An advantage of the MRAM architecture according to the present invention is that it allows lower power consumption than prior art devices and high selectivity during writing. The present invention also provides a method of writing a value in a matrix of magnetoresistive memory cells (30) according to the present invention, and a method of manufacturing such magnetoresistive memory cells (30).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.