Programmable logic device memory elements with elevated power supply levels
US7277351B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2006 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Apr 3, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17784
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Programmable logic device integrated circuits are provided. The programmable logic device integrated circuits contain programmable core logic powered at a programmable core logic power supply voltage. Programmable logic device configuration data is loaded into the memory elements to configure the programmable core logic to perform a custom logic function. During normal operation the memory elements may be powered with a power supply voltage that is larger than the programmable core logic power supply voltage. During data loading operations, the memory elements may be powered with a power supply voltage equal to the programmable core logic power supply voltage. Data loading and reading circuitry loads data into the memory elements and reads data from the memory elements. Address signals are generated by the data loading and reading circuitry. The address signals may have larger voltage levels during data writing operations than during read operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.