Hierarchical scheduler inter-layer eligibility deferral
US7277448B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2003 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Feb 16, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Conventional schedulers propagate entries by either polling until an entry is ready, or alternatively, by attaching a so-called “readiness time” to entries. A scheduler which recognizes the readiness time avoids consuming a parent schedule with polling, or with burdening entries with a future readiness time. The system of the present invention employs a deferral queue for deferring entries in response to pop requests from a parent schedule. The child schedule defers entries via the deferral queue when it is not ready to push an entry to the parent schedule, and sets the readiness time corresponding to the entry. Upon the expiration of the readiness time, the child schedule redetermines whether to push the deferred entry corresponding to the deferral queue or optionally to push an interim entry having since arrived. Accordingly, a child schedule receiving a pop requests retains the ability to push an entry at an earlier or later readiness time, and further retains the ability to reconsider which entry to push.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.