Cache eviction technique for reducing cache eviction traffic
US7277992B2 · kind B2 · utility
6Cited by
3References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2005 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Apr 6, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an inclusive cache hierarchy based on the cache coherency traffic generated between an upper level cache and lower level caches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.