Test head utilized in a test system to perform automated at-speed testing of multiple gigabit per second high serial pin count devices
US7278079B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 30, 2002 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Aug 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31903
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A portion of a test head utilized to perform simultaneous automated at-speed testing of a plurality of devices that generate serial data signals having gigabit per second baud rates. The portion of the test head includes connection sections that couple an external testing system to the portion of the test head, a restricted section positioned between said connection sections, a device interface board (DIB) having a device under test (DUT) holding section that secures the devices, said DIB positioned below said restriction section and a multi-layered rider board coupled to the devices via a coupling section, said rider board forming signal paths to route testing signals between at least the devices and the external testing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.