Method and apparatus for reducing redundant data in a layout data structure
US7278121B2 · kind B2 · utility
4Cited by
9References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2004 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Feb 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The method and apparatus in accordance with the present invention reduces the data size of a layout data structure by reducing the amount of electrically redundant interconnects within a bank of interconnects. Electrically redundant interconnects are the repetitive interconnects within a bank of interconnects which do not contribute to the understanding of the IC. Therefore, a number of these interconnects may be deleted from the banks in the layout data structure, provided that enough interconnects remain to maintain the electrical connectivity and the visual representation of the bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.