Methods and apparatus for compiling instructions for a data processor
US7278137B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2002 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Aug 13, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4434
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus optimized for compiling instructions in a data processor are disclosed. In one aspect, a method of address calculation is disclosed, comprising operating a compiler to generate at least one instruction; canonicalizing the address calculation in a plurality of different approaches: in one exemplary embodiment, the first approach comprises canonicalizing the “regular” 32-bit instruction addressing modes, and the second for the “compressed” 16-bit instruction addressing modes. In another aspect, a plurality of functions (up to and including all available functions) are called indirectly to allow addresses to be placed in a constant pool. Improved methods for instruction selection, register allocation and spilling, and instruction compression are provided. An improved SoC integrated circuit device having an optimized 32-bit/16-bit processor core implementing at least one of the foregoing improvements is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.