Thin film transistor array substrate and method of fabricating the same
US7279370B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2004 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Mar 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136236
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor array substrate device includes a gate line formed on a substrate, a data line crossing the gate line with a gate insulating pattern position therebetween, a thin film transistor at a crossing of the gate line and the data line, a pixel electrode formed at a pixel region defined by the crossing of the gate line and the data line and connected to the thin film transistor, a gate pad part having a lower gate pad electrode connected to the gate line and an upper gate pad electrode connected to the lower gate pad electrode, a data pad part having a lower data pad electrode connected to the date line and an upper data pad electrode connected to the lower data pad electrode, and a passivation film pattern formed at a region besides the region including the pixel electrode, the upper data pad electrode, and the upper gate pad electrode, wherein the pixel electrode is formed on the gate insulating pattern of the pixel region exposed by the passivation film pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.