Double-sided extended drain field effect transistor
US7279757B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2004 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Dec 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
A double-sided extended drain field effect transistor that includes a gate terminal overlying a channel region in a substrate. The substrate includes a drain region of a first carrier type that is laterally separated from the channel region by a first RESURF region of the first carrier type, and a source region of the first carrier type that is laterally separated from the channel region by a second RESURF region of the first carrier type. Regions of the first carrier type may also be disposed laterally adjacent to the source and drain regions on the opposite lateral side as compared to the RESURF regions. This configuration improves the reverse bias breakdown voltage of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.