Semiconductor device for overvoltage protection
US7279768B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2006 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Apr 3, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across an upper surface of the N-type buried diffusion layer over a wide range to form a PN junction region for an overvoltage protection. A P-type diffusion region is formed so as to be connected to the P-type buried diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. This structure makes it possible to prevent a concentration of a breakdown current and protect the semiconductor device from an overvoltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.