Delay chain integrated circuits having binary-weighted delay chain units with built-in phase comparators therein
US7279938B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 18, 2006 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Sep 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Delay-locked loop integrated circuits include a delay chain having a plurality of delay chain units. The delay chain may be a binary-weighted delay chain and the delay chain units may be arranged in ascending or descending order (e.g., x1, x2, x4, x8, . . . ) according to delay. Each of the plurality of delay chain units may include a respective phase comparator. Each phase comparator is configured to identify whether a delay provided by the corresponding delay chain unit exceeds a fraction of a period of a reference clock signal applied to an input of the delay chain. This fraction of a period may be equivalent to one-half or other percentage of a period of the reference clock signal. The phase comparators with the delay chain units operate to generate a multi-bit delay value signal, which is provided to a delay chain control circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.