Circuit for differential current sensing with reduced static power
US7279939B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2005 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Sep 20, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356165
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Returning to FIG. 2, sense circuit 201 represents the circuit that must sense the signaling on an interconnect. NMOS device 202 is always on so that there is a continuous path to ground whenever PMOS driver 204 is on. Since leakage power is an order of magnitude less than static and dynamic power it can be omitted for clarity, although it should be noted that dynamic power increases with respect to line length since the interconnect capacitance increases as line length increases. Static power is due to flow of static current across the two resistances shown in FIG. 2, interconnect resistance 206 and the resistance of transistors 102 and 104 from FIG. 1, represented by the resistance of equivalent NMOS transistor 208 of FIG. 2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.