Method and system for high frequency clock signal gating
US7279950B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2005 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Sep 30, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal responsive to a first clock signal pulse negative half. The buffer provides second and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse as a buffer clock signal output to a second buffer stage in a second stage clock path, each having the nominal clock amplitude and the nominal clock pulse width of the clock signal without jitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.