Method and apparatus for biasing a metal-oxide-semiconductor capacitor for capacitive tuning
US7280002B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2005 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Aug 6, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is presented for generating a reference voltage that biases a metal-oxide-semiconductor (MOS) transistor used as a varactor in capacitive tuning applications. In one embodiment, a biasing circuit is implemented. The biasing circuit comprises a diode-clamped FET and an element coupled to the diode-clamped FET at a connection point. The element produces a constant current through the diode-clamped FET. A voltage is produced at the connection point. The voltage is one gate overdrive plus a threshold voltage above ground or one gate overdrive plus a threshold voltage below VDD. Establishing a threshold voltage in this way enables the biasing circuit to track an ideal voltage of a varactor that is coupled to the biasing circuit through the threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.