Low inductance high ESR capacitor
US7280342B1 · kind B1 · utility
13Cited by
10References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2006 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Dec 15, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01G4/30
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A low inductance multi-layer capacitor. The capacitor comprises interleaved parallel internal electrode plates with dielectric there between. Each internal electrode plate comprises two lead-out tabs and is generally T shaped. A first external electrode terminal is electrically connected to the lead-out tabs of the even internal electrode plates, and a second external electrode terminal is electrically connected to the lead-out tabs of the odd internal electrode plates. The external electrode terminals are on a common first exterior surface and a common opposing second exterior surface of the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.