CAM cells and CAM matrix made up of a network of such memory cells
US7280378B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2006 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Jul 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory (CAM) includes first and second memory circuits and a comparison circuit. The first memory circuit includes first and second sets of transistors for the storage of first and second compare data. The second memory circuit includes first and second sets of transistors for the storage of enabling or disabling data. The comparison circuit includes first and second sets of comparison transistors which respectively provide for the comparison of the first and second compare data with first and second input data under the control of an output signal from the second memory circuit. The transistors of the first and second sets of transistors of the memory circuits each includes a transistor of a first conductivity type and a transistor of a second conductivity type. The transistors of the second conductivity type are formed on the same first active zone of the semiconductor substrate. The first and second sets of comparison transistors of the comparison circuit are formed in separate active zones, respectively, which are mutually separated by the first active zone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.