Semiconductor memory device and a method for arranging signal lines thereof
US7280383B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2005 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Oct 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a semiconductor memory device and a method for arranging signal lines thereof. The semiconductor memory device including a first memory cell array, an IO control circuit and a second memory cell array arranged between the first memory cell array and the IO control circuit, includes: first IO signal lines for transmitting data between the first memory cell array and the IO control circuit, wherein the first IO signal lines are connected to first data loading locations of the first memory cell array and extend in a straight line to the IO control circuit; and second IO signal lines for transmitting data between the second memory cell array and the IO control circuit, wherein the second IO signal lines are connected to first data loading locations of the second memory cell array and extend to the IO control circuit, wherein lengths of the first IO signal lines starting from the first data loading locations of the first memory cell array to the IO control circuit are identical to lengths of the second IO signal lines starting from the first data loading locations of the second memory cell array to the IO control circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.