Method for hardware reduction in echo canceller and near-end crosstalk canceller
US7280493B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 25, 2002 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Oct 2, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/23
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for hardware reduction in the echo canceller and the near-end crosstalk canceller. The method applies an N (N is a positive integer) times divide frequency sampling operation onto the input data list of the echo canceller first (and the near-end crosstalk canceller). Then, it applies an N times multiply frequency sampling operation onto the output data list of the echo canceller (and the near-end crosstalk canceller) to generate a multiplied frequency data list. Afterwards, a low pass filter operation is applied to the multiplied frequency data list to generate a low pass data list to eliminate the echo signal (and the near-end crosstalk signal). The present invention reduces the number of the taps in the echo canceller and the near-end crosstalk canceller by using the digital signal process technique. Therefore, the area of the whole communication IC occupied by the echo canceller and the near-end crosstalk canceller can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.